320
|
Topic |
Relevant Chapter(s) / Appendix |
|---|---|
|
Course logistics, Overview, Performance |
Chapter 1 – Fundamentals of Quantitative Design and Analysis |
|
General ISA, RISC‑V ISA |
Appendix A – Instruction Set Principles |
|
RISC‑V Single-cycle |
Appendix C – Pipelining: Basic and Intermediate Concepts |
|
RISC‑V Pipeline |
Appendix C – Pipelining: Basic and Intermediate Concepts |
|
RISC‑V Pipeline Interrupts |
Appendix C (plus instructor supplements) |
|
Caches & Cache Controllers |
Chapter 2 – Memory Hierarchy DesignAppendix B – Review of Memory Hierarchy |
|
Virtual Memory |
Appendix L – Advanced Concepts on Address Translation |
|
Dynamic Scheduling |
Chapter 3 – Instruction-Level Parallelism and Its Exploitation |
|
Multicore Synchronization |
Chapter 5 – Thread-Level Parallelism |
|
Multicore Coherence |
Chapter 5 – Thread-Level Parallelism |
|
Multicore Consistency Models |
Chapter 5 – Thread-Level Parallelism |
|
Multithreading |
Chapter 5 – Thread-Level Parallelism |
|
GPUs and Vector Processors |
Chapter 4 – Data-Level Parallelism in Vector, SIMD, and GPU ArchitecturesAppendix G – Vector Processors in More Depth |
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